Last week, I posted a puzzle which asked how you could replicated NOT gate functionality using only AND gates. Here is probably the most simple way, using only two AND gates:

Robin asked if the solution involved some sort of hardware trickery and, in a sense, I suppose it does. The solution takes advantage of the power and ground connections to the gate devices to augment the effective logic truth table. The truth table for a standard AND gate is usually shown like this:

A B | Q
----+--
0 0 | 0
0 1 | 0
1 0 | 0
1 1 | 1

where A and B are the two inputs and Q is the output of the gate. The output only goes high if the inputs are both high. This is the abstract logic that is implemented by a physical AND gate. Unfortunately, there is no way to combine any number of these truth tables to produce a NOT function.

However, an actual physical AND gate requires electrical power to do its thing and you can think of the power and ground connections to the gate hardware as "inputs." When you take these inputs into account, let's call them P and G, you get the following truth table:

P G A B | Q
--------+--
0 0 0 0 | Z
0 0 0 1 | Z
0 0 1 0 | Z
0 0 1 1 | Z
0 1 0 0 | X
0 1 0 1 | X
0 1 1 0 | X
0 1 1 1 | X
1 0 0 0 | 0
1 0 0 1 | 0
1 0 1 0 | 0
1 0 1 1 | 1
1 1 0 0 | Z
1 1 0 1 | Z
1 1 1 0 | Z
1 1 1 1 | Z

where Z indicates a high-impedance output and X indicates the gate has been destroyed. The high-impedance state is what you get when the device is not powered, which happens any time the power and ground connections are at the same voltage. The X conditions are reached when the ground voltage is high and the power voltage is low, a.k.a. reversing power and ground, a.k.a. el bortus de chip.

The above schematic takes advantage of the high-impedance states available in the expanded truth table to achieve the logical NOT operation. In a sense, this is a "stupid hardware trick" because the power connections to logic hardware are not generally driven conditionally as part of combinatorial logic... but it is a valid circuit.